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Guangzhou Gootite Electronic Tech Co.,Ltd.

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What is the three anti-paint, which is the three anti-paint?
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What is the three anti-paint, which is the three anti-paint?

Release time:
2019-03-17 23:12
What are the three anti-paints? It should be said that there is no definition in the strict sense. The word "three" takes the meaning of "more" in ancient Chinese, that is, the intention of multi-directional protection. The basic function of three-proof paint in daily application is to have waterproof, moisture-proof and dust-proof "three-proof" performance. In addition, it has the properties of resistance to thermal shock, aging, radiation, salt spray, ozone corrosion, vibration, flexibility, and adhesion. Because of its low technical content and low price, it is low-end products. The application is more extensive.

Three-coating is a specially formulated coating designed to protect circuit boards and their associated equipment from environmental degradation, thereby increasing and extending life and ensuring safety and reliability. Under realistic conditions, such as chemical environment (fuel, coolant, etc.), vibration, high dust, salt spray, humidity and high temperature, the circuit board may cause corrosion, softening, deformation, mildew and other problems, resulting in circuit board circuit failure. . The three anti-paint is applied to the exterior of the circuit board to form a pliable film having a thickness of about 50-100 microns. It protects the circuit from damage under relatively harsh conditions.

The application range of three anti-paints is very wide. The civilian appliances such as mobile phones and TVs are only a small part. The application of three anti-paints has been extended to the aerospace, medical and automotive industries. In the aerospace industry, the requirements for electronic equipment are very strict. In the extreme environment, the demand for three anti-paints that can protect electronic equipment will be very broad.

In some harsh environments, the board is prone to failure. Once the board fails, the consequences will roll like a snowball. For example in a humid environment. Moisture often attacks the board, and excessive moisture can significantly reduce the insulation resistance between the conductors, causing undesirable consequences.
Detailed interpretation of SMT patch assembly methods and processing
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Detailed interpretation of SMT patch assembly methods and processing

Release time:
2019-03-17 23:12
As the most popular placement technology in the electronics industry, SMT chip processing and assembly has a very wide range of applications in the market.

The most common SMT patch assembly methods can be divided into single-sided assembly, single-sided mixing, double-sided assembly, and double-sided mixing. Among them, the types of circuit substrates used for single-sided assembly and double-sided assembly are single-sided PCB and double-sided PCB, respectively, and the mixing method is more complicated. Single-sided mixing can be divided into first-paste method and post-paste method, while double-sided assembly is divided into SMC/SMD and FHC ipsilateral mode and SMC/SMD and iFHC different side modes, so we will not introduce them one by one. .


Next, let's take a look at the process flow of SMT patch assembly. Different assembly methods correspond to different assembly processes, and a reasonable assembly process is also a guarantee of assembly quality and assembly efficiency. After the assembly method is determined, the process flow can be determined for the actual product and the specific equipment. Due to limited time, only the process of single and double-sided mixing is introduced here:


1. Single-sided mixing: incoming material inspection + PCB A-side silk screen solder paste (red glue) + patch + A surface reflow (cure) + cleaning + plug-in + wave peak + cleaning + detection + rework.


2, double-sided mixing: incoming material detection + PCB B-side silk screen solder paste (red plastic) + patch + B surface reflow (curing) + cleaning + flip + A surface silk screen solder paste (red plastic) + patch +B surface reflow (curing) or (DIP + crest) + cleaning + detection + rework.


Seeing here, everyone should know more about the SMT patch assembly method and process flow, or not? For customers who need it, only by selecting the SMT patch assembly and processing factory, can we guarantee the quality and delivery of electronic products, and really save the effort.
Why is the SMT red glue process less and less used?
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Why is the SMT red glue process less and less used?

Release time:
2019-03-17 23:12
In the SMT patch processing plant, the solder paste process has become the mainstream process, and as the older red glue process has been used less and less, why is this?

First, the red glue is not conductive, the solder paste can conduct electricity

We know that the role of red glue is mainly to fix the role, while the solder paste has a fixed effect and is also conductive, and the soldering effect of the red glue does not seem to have a beautiful soldering effect.


Second, the conditions for the use of red plastic technology are increasingly limited

The properties of red glue are heat-cured, so they are usually used for wave soldering to prevent components from falling. Nowadays, the density between components is getting higher and higher, and the components are getting smaller and smaller. At this time, when the wave soldering is over, it is easy to appear tin and short circuit.

Third, the use of red plastic process maintenance difficulties

We know that red glue is heat-cured and will become very hard after curing. When it is repaired and baked, it is easy to carbonize and maintenance is relatively difficult.

Fourth, the improvement of DIP fixture for solder paste process

When the red glue process is over wave soldering, the components of the patch are exposed to the outside. At this time, in the high temperature state, some components may be damaged, and the solder paste process has a special fixture, in the case of wave soldering. The part of the patch is blocked, only the pins of the plug-in are exposed, and the components of the patch can be well protected from damage.

Nowadays, electronic products are increasingly pursuing functionalization and miniaturization, which poses great challenges to SMT technology, and the requirements for welding are getting higher and higher. The red glue process cannot keep up with the development of the times due to its own shortcomings. Requirement that the red glue process is becoming less and less used in SMT factories is an inevitable result.
Development status of wafer level packaging technology
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Development status of wafer level packaging technology

Release time:
2019-03-17 23:12
With the development of IC chip technology, chip packaging technology has also reached a new level, and system integration can be realized on a single chip.

Among the many new packaging technologies, wafer-level packaging technology is the most innovative and most eye-catching, and is a symbol of revolutionary breakthroughs in packaging technology. The concept of wafer-level packaging technology is to fabricate CSP packaging technology on the entire wafer, which is to complete most of the packaging work at the wafer level. Therefore, the wafer-level package structure can omit the step of flip chip technology dispensing. At present, an elastomer or an elastomer-like body can be used to offset the stress, and the process of these elastomers can be completed on the entire wafer. Eliminates the complicated process of dispensing separate components. The design concept of square wafer packaging technology is to increase the distance between components and substrates, that is, to select a larger tin-lead solder ball to achieve conductivity. The existing wafer-level packaging technology uses re-layout technology to add The spacing of the large tin-lead solder balls is such as to increase the volume of the tin-lead solder balls, thereby reducing and withstanding the stress caused by the difference in thermal expansion between the substrate and the components, thereby improving the reliability of the components.

Wafer-level packaging and wafer-level chip-scale packaging (WLCSP) are the same concept. It is a breakthrough in chip-scale packaging. It represents a type of package that still exists as a wafer after the completion of a circuit package. The main reason is that it can reduce the package size to the same size as IC chips and the cost of processing. Wafer-level packaging is currently growing at an alarming rate, with an average annual growth rate (CAGR) of 210%. The growing devices are primarily integrated circuits, passive components, high-performance memories, and devices with fewer pin counts.

There are currently five proven process technologies available for wafer bumps, each with its own advantages and disadvantages. Among them, gold wire post bumps and electrolytic or electroless gold plating bumps are mainly used for packages with a small number of pins (generally less than 40). Applications include glass flip chip (COG) and soft film flip chip (COF). ) and RF modules. Due to the high cost and long process time of such technical materials, it is not suitable for packages with many I/O pins. Another technique is to place the solder balls first and then reflow the pre-formed solder balls. This technique is suitable for packages with up to 300 pins. The two most commonly used wafer bump processes are electrolytic or chemically plated solders, as well as solder paste printing using high precision imprinting platforms.

One of the advantages of printed solder paste is the low investment in equipment, which allows many wafer bump processing manufacturers to enter the market and serve semiconductor manufacturers. As WLP is gradually accepted by the commercial market, the demand for new wafer bump professional processing services continues to grow rapidly. Indeed, most wafer bumping plants are predicated on printing capabilities and offer one or more other technologies. Many people in the industry believe that solder paste printing technology will dominate the application of most wafer bumps.